An n-bit parallel-conversion-type analog-to-digital converter (also known as a Flash ADC or a flashing ADC) adopts 2n comparators to compare analog signals Vin with 2n reference signals, and then encodes outputs of the comparators to quantize the analog signals. In general, the 2n reference signals are evenly distributed in a certain signal range, which is called a quantization range.
FIG. 1 is a circuit diagram of a 3-bit flash ADC which comprises eight serially-connected resistors (101, 102, 103, 104, 105, 106, 107 and 108), seven parallel operating comparators (COM1, COM2, COM3, COM4, COM5, COM6 and COM7), an encoding circuit 128, an analog signal input port Vin, a reference voltage port REFA, a reference voltage port REFB, and digital output ports D0, D1 and D2.
The reference voltage port REFA is connected to the positive end of the resistor 108; the negative end of the resistor 108 is connected to the positive end of the resistor 107; the negative end of the resistor 107 is connected to the positive end of the resistor 106; the negative end of the resistor 106 is connected to the positive end of the resistor 105; the negative end of the 105 is connected to the positive end of the resistor 104; the negative end of the resistor 104 is connected to the positive end of the resistor 103; the negative end of the resistor 103 is connected to the positive end of the resistor 102; the negative end of the resistor 102 is connected to the positive end of the resistor 101; and the negative end of the resistor 101 is connected to the reference voltage port REFB.
The maximum value and the minimum value in a voltage quantization range are added to the reference voltage port REFA and the reference voltage port REFB, respectively, so that reference voltages V7, V6, V5, V4, V3, V2 and V1 are generated at the negative ends of the resistors 108, 107, 106, 105, 104, 103, and 102. The non-inverting ends of comparators COM7, COM6, COM5, COM4, COM3, COM2, and COM1 are connected together to receive the analog signals from the port Vin, and the inverting ends of the comparators are configured to receive the reference voltages V7, V6, V5, V4, V3, V2 and V1, respectively.
The resistance values of the resistors 101, 102, 103, 104, 105, 106, 107 and 108 are the same. There is no current flowing through the inverting ends of the comparators COM7, COM6, COM5, COM4, COM3, COM2, and COM1, so that the reference voltages V7, V6, V5, V4, V3, V2 and V1 are evenly distributed between the voltage ports REFA and REFB, as shown in FIG. 2.
As can be seen from FIG. 2, the reference voltages V1, V2, V3, V4, V5, V6 and V7 divide a signal interval [REFB, REFA] into eight equal intervals. When the signal at the analog signal input port Vin changes from low to high and exceeds a reference voltage V1 (i=1 to 7), the output of the corresponding comparator COMi is inverted. That is, the outputs of the comparators COM1, COM2, COM3, COM4, COM5, COM6 and COM7 identify and encode the eight signal sections in FIG. 2.
Those skilled in the art know that output encodes of the comparators COM1, COM2, COM3, COM4, COM5, COM6 and COM7 in FIG. 1 are thermometer codes whose disadvantages lie in that a large number of signal lines are required, and the encoding efficiency is very low as lots of codes are wasted. The output ends of the comparators COM1, COM2, COM3, COM4, COM5, COM6 and COM7 are connected to the encoding circuit 128 to convert the thermometer codes to binary codes, so that 3-bit binary codes are output from the output ports D0, D1 and D2.
In the actual implementation of the circuit in FIG. 1, the comparator has an offset. Especially, the offset of the comparator based on the CMOS process is more severe. Thus, an actual reference voltage of the comparator in FIG. 1 is a sum of a reference voltage generated by a resistor string and an offset voltage, as shown in FIG. 3. In FIG. 3, voltage sources VO1, VO2, VO3, VO4, VO5, VO6, and VO7 represent the offset voltages of the comparators COM1, COM2, COM3, COM4, COM5, COM6 and COM7, respectively. In this way, a reference voltage actually seen by a comparator COMi (i=1 to 7) is (Vi+VOi). The offset voltage VOi (i=1 to 7) has randomness. For different comparators, process conditions and chips, offset voltages are different. A circuit designer can only obtain some statistical results instead of predicting a specific value of the offset voltage.
When the accuracy of the flash ADC is quite high (such as 6-bit or 8-bit conversion accuracy), a difference between adjacent reference voltages is quite small. If the comparator offset voltage in FIG. 3 causes the reference voltage seen by the comparator COMi (i=1 to 7) to be greater than the reference voltage seen by the comparator COMi+1, the flash ADC will lose a code. As shown in FIG. 4, due to the offset, the reference voltage (V4+VO4) seen by the comparator COM4 is smaller than the reference voltage (V3+VO3) seen by the comparator COM3. Thus, when the analog input signal Vin in FIG. 3 changes from small to large, the comparator COM4 reverses first, and then the comparator COM3 reverses, resulting in code missing.
A traditional method of reducing the comparator offset is to use a larger device. However, this will increase power consumption of a circuit and reduce the operating speed of the circuit.
In the present invention, through a self-correct process, an offset voltage of a comparator is corrected through a reference signal externally connected with a chip or generated inside the chip, so that code missing in the flash ADC is eliminated, and the performance indexes of a DNL and INL are improved. In addition, with the offset correction, the comparator can be implemented through a smaller device, thereby improving the speed of the comparator.